This video introduces the Vivado environment, illustrating how to create a project, add a source file and a test bench. Simulate the code and view the output waveforms and log file. The session deals with the simulation of combinational logic circuits. Structural, dataflow and behavioral Verilog codes for logic gates, half adder, multiplexer, full adder, 4 to 1 mux, and prime number detector are simulated, for example.