Placement VLSI in Physical Design

Engineering

2023-11-19

Lessons List

PD Lec 31 Introduction to Placement | VLSI | Physical Design

PD Lec 32 Placement of std cells | VLSI | Physical Design

PD Lec 33 Placement and Optimization | VLSI | Physical Design

PD Lec 34 place opt understanding | VLSI | Physical Design

PD Lec 35 Scan Chain Optimization | VLSI | Physical Design

PD Lec 36 Cell Density of std cells | VLSI | Physical Design

PD Lec 37 Pin Density of std cells | VLSI | Physical Design

PD Lec 38 Global Route Congestion | VLSI | Physical Design

PD Lec 39 CMOS Latch Up | VLSI | Physical Design

PD Lec 40 Well Tap Cell | VLSI | Physical Design

PD Lec 41 Tie Cell | tie low| tie high | VLSI | Physical Design

PD Lec 42 SVT LVT HVT Cell variants | VLSI | Physical Design

PD Lec 43 Timing Fixes in placement | Part 1 | VLSI | Physical Design

PD Lec 44 Timing Fixes in placement | Part 2 | VLSI | Physical Design

PD Lec 45 Spare Cells | Physical Only Cells | VLSI | Physical Design

PD Lec 46 Useful Skew | Timing Fixes in placement | VLSI | Physical Design

PD Lec 47 concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design

PD Lec 48 Interview Questions | placement | VLSI | Physical Design

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4.6

28 Reviews

Sangamithra A M

NICE 2025-05-31

Chandrika G S

Good 2025-05-29

Namachivayam

The course content appears well-aligned with current industry needs. Courses provide hands-on experience with tools like Cadence, Synopsys, and Mentor Graphics, which are widely used in the semiconductor industry 2025-05-28

SURYA P

good 2025-05-28

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Placement VLSI in Physical Design

Engineering

PD Lec 31 Introduction to Placement | VLSI | Physical Design

PD Lec 32 Placement of std cells | VLSI | Physical Design

PD Lec 33 Placement and Optimization | VLSI | Physical Design

PD Lec 34 place opt understanding | VLSI | Physical Design

PD Lec 35 Scan Chain Optimization | VLSI | Physical Design

PD Lec 36 Cell Density of std cells | VLSI | Physical Design

PD Lec 37 Pin Density of std cells | VLSI | Physical Design

PD Lec 38 Global Route Congestion | VLSI | Physical Design

PD Lec 39 CMOS Latch Up | VLSI | Physical Design

PD Lec 40 Well Tap Cell | VLSI | Physical Design

PD Lec 41 Tie Cell | tie low| tie high | VLSI | Physical Design

PD Lec 42 SVT LVT HVT Cell variants | VLSI | Physical Design

PD Lec 43 Timing Fixes in placement | Part 1 | VLSI | Physical Design

PD Lec 44 Timing Fixes in placement | Part 2 | VLSI | Physical Design

PD Lec 45 Spare Cells | Physical Only Cells | VLSI | Physical Design

PD Lec 46 Useful Skew | Timing Fixes in placement | VLSI | Physical Design

PD Lec 47 concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design

PD Lec 48 Interview Questions | placement | VLSI | Physical Design

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Placement VLSI in Physical Design

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