VLSI Physical Design basics

Engineering

2023-11-19

Lessons List

PD Lec 1 Introduction to Physical Design | Tutorial | VLSI

PD Lec 2 CMOS Basics part 1 | Tutorial | VLSI | Physical Design

PD Lec 3 CMOS Basics part 2 | Tutorial | VLSI | Physical Design

PD Lec 4 CMOS Basics part 3 | Tutorial | VLSI | Physical Design

PD Lec 5 Logic Gate Conversion | Tutorial | VLSI | Physical Design

PD Lec 6 CMOS basics part 4 | Tutorial | VLSI | Physical Design

PD Lec 7 Physical Design Inputs Overview | Tutorial | VLSI | Physical Design

PD Lec 8 Netlists | PD Inputs part 2 | VLSI | Physical Design

PD Lec 9 Timing Library | libs | PD Inputs part 3 | VLSI | Physical Design

PD Lec 10 LEF File | PD Inputs part 4 | VLSI | Physical Design

PD Lec 11 Constraints File | PD Inputs part 4 | VLSI | Physical Design

PD Lec 12 Technology File | Tech File | PD Inputs part 5 | VLSI | Physical Design

PD Lec 13 DEF File | PD Inputs part 6 | VLSI | Physical Design

PD Lec 14 Import Design | Milky Way Library | VLSI | Physical Design

PD Lec 15 Floor planning part 1 | VLSI | Physical Design

PD Lec 16 Floor planning part 2 | VLSI | Physical Design

PD Lec 17 Floorplanning IO Placement part 3 | VLSI | Physical Design

PD Lec 18 Macro Placement Floor planning part 4 | VLSI | Physical Design

PD Lec 19 Macro Placement Guidelines Floor planning part 5 | VLSI | Physical Design

PD Lec 20 Macro Channel Spacing Estimation Floor planning part 6 | VLSI | Physical Design

PD Lec 21 Macro Placement Guidelines Floor planning part 7 | VLSI | Physical Design

PD Lec 22 Blockages and Keep out Margin | Floor planning | VLSI | Physical Design

PD Lec 23 Macro placement issues | | Floor planning | VLSI | Physical Design

PD Lec 24 Power planning and power mesh creation| Floor planning | VLSI | Physical Design

PD Lec 25 Physical Only Cells | Floor planning | VLSI | Physical Design

PD Lec 26 Sanity Checks 1 | Floor planning | VLSI | Physical Design

PD Lec 27 Sanity Checks 2 | Floor planning | VLSI | Physical Design

PD Lec 28 Sanity Checks 3 | Floor planning | VLSI | Physical Design

PD Lec 29 Cell Orientation and Flipping | Placement | VLSI | Physical Design

PD Lec 30 Interview Questions | VLSI | Physical Design

PD Lec 31 Introduction to Placement | VLSI | Physical Design

PD Lec 32 Placement of std cells | VLSI | Physical Design

PD Lec 33 Placement and Optimization | VLSI | Physical Design

PD Lec 34 place opt understanding | VLSI | Physical Design

PD Lec 35 Scan Chain Optimization | VLSI | Physical Design

PD Lec 36 Cell Density of std cells | VLSI | Physical Design

PD Lec 37 Pin Density of std cells | VLSI | Physical Design

PD Lec 38 Global Route Congestion | VLSI | Physical Design

PD Lec 39 CMOS Latch Up | VLSI | Physical Design

PD Lec 40 Well Tap Cell | VLSI | Physical Design

PD Lec 42 SVT LVT HVT Cell variants | VLSI | Physical Design

PD Lec 41 Tie Cell | tie low| tie high | VLSI | Physical Design

PD Lec 43 Timing Fixes in placement | Part 1 | VLSI | Physical Design

PD Lec 44 Timing Fixes in placement | Part 2 | VLSI | Physical Design

PD Lec 45 Spare Cells | Physical Only Cells | VLSI | Physical Design

PD Lec 46 Useful Skew | Timing Fixes in placement | VLSI | Physical Design

PD Lec 47 concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design

PD Lec 48 Interview Questions | placement | VLSI | Physical Design

PD Lec 49 Introduction to CTS | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 50 Clock Tree Synthesis | CTS | VLSI | Physical Design

PD Lec 51 How to balance skew and latency | CTS | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 52 CTS Algorithms | CTS | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 53 CTS Constraints | Spec File | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 54 CTS Exceptions | Float pin | Stop Pin | Exclude Pin | VLSI | Physical Design

PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design

PD Lec 56 Clock Gating Checks | CGC Paths | CTS | VLSI | Physical Design

PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design

PD Lec 58 Integrated Clock Gates | ICG | CTS | VLSI | Physical Design

PD Lec 59 Master Generated and Virtual Clocks | Type of clocks | VLSI | Physical Design

PD Lec 60 What is crosstalk | CTS | VLSI | Physical Design

PD Lec 61 Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design

PD Lec 62 CTS Analysis | VLSI | Physical Design

PD Lec 63 Post CTS Optimization | VLSI | Physical Design

PD Lec 64 Skew Groups | CTS | VLSI | Physical Design

PD Lec 65 Introduction to Routing | VLSI | Physical Design

PD Lec 66 Routing Concepts | VLSI | Physical Design

PD Lec 67 Global and Detail Routing | VLSI | Physical Design

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Good		41 Reviews
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4.5

103 Reviews

VEERA SHANKAR GANGARAPU

The VLSI Design Basics course provided a solid foundation in core concepts such as CMOS design, digital logic, and semiconductor fundamentals. The content was well-structured, clear, and effective for building fundamental understanding

2026-03-31

Gopisetti NagaRaju

very good

2026-03-30

KATIKILA PRADEEP

good

2026-03-18

Gurla Sudharani

Good

2026-01-17

BODDU LEELA SAI KRISHNA

Very helpful course.
The concepts are explained clearly and in a simple way.

2026-01-07

Jampani Bhavannarayana

great experience

2026-01-05

Mallika.R

Very helpful

2025-12-28

VINOD PATIL

This course is giving me a great knowladge about VLSI Physical Design Basics, and thanks for the MindLuster

2025-12-17

Meenakshi Sanagala

very helpful

2025-12-16

Ramadas Vijendra

Very good course for beginners

2025-12-11

Shruthi Muthyala

Ok

2025-12-03

CHANDRU R

good

2025-12-03

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VLSI Physical Design course in hindi, in this course explores the intricacies of chip layout, placement, and routing for efficient and high-performance integrated circuit design

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लिनक्स को शुरू से चरण दर चरण सीखें कक्षा 6 संस्कृत दीपकम रिवीजन कक्षा 7 नागरिक शास्त्र SST रिवीजन CBSE कक्षा 7 इतिहास SST रिवीजन CBSE कक्षा 7 भूगोल SST रिवीजन CBSE कक्षा 12 अर्थशास्त्र वन शॉट रिवीजन CBSE कक्षा 12 रसायन विज्ञान CBSE परीक्षा के लिए कक्षा 12 रसायन विज्ञान CBSE परीक्षा के लिए कक्षा 10 गणित CBSE बोर्ड परीक्षा के लिए सीबीएसई परीक्षा के लिए कक्षा 12 जीवविज्ञान सीबीएसई परीक्षा के लिए कक्षा 12 जीवविज्ञान कक्षा 7 नागरिक शास्त्र SST वर्कशीट्स सीबीएसई बोर्ड परीक्षा के लिए कक्षा 12 भौतिकी कक्षा 8 इतिहास SST वर्कशीट अभ्यास कक्षा 7 इतिहास SST वर्कशीट अभ्यास कक्षा 8 भूगोल SST वर्कशीट कक्षा 7 भूगोल SST वर्कशीट कक्षा 8 नागरिक शास्त्र SST वर्कशीट CBSE बोर्ड परीक्षा के लिए कक्षा 10 विज्ञान कक्षा 10 सामाजिक विज्ञान अंग्रेज़ी माध्यम

VLSI Physical Design basics

Engineering

PD Lec 1 Introduction to Physical Design | Tutorial | VLSI

PD Lec 2 CMOS Basics part 1 | Tutorial | VLSI | Physical Design

PD Lec 3 CMOS Basics part 2 | Tutorial | VLSI | Physical Design

PD Lec 4 CMOS Basics part 3 | Tutorial | VLSI | Physical Design

PD Lec 5 Logic Gate Conversion | Tutorial | VLSI | Physical Design

PD Lec 6 CMOS basics part 4 | Tutorial | VLSI | Physical Design

PD Lec 7 Physical Design Inputs Overview | Tutorial | VLSI | Physical Design

PD Lec 8 Netlists | PD Inputs part 2 | VLSI | Physical Design

PD Lec 9 Timing Library | libs | PD Inputs part 3 | VLSI | Physical Design

PD Lec 10 LEF File | PD Inputs part 4 | VLSI | Physical Design

PD Lec 11 Constraints File | PD Inputs part 4 | VLSI | Physical Design

PD Lec 12 Technology File | Tech File | PD Inputs part 5 | VLSI | Physical Design

PD Lec 13 DEF File | PD Inputs part 6 | VLSI | Physical Design

PD Lec 14 Import Design | Milky Way Library | VLSI | Physical Design

PD Lec 15 Floor planning part 1 | VLSI | Physical Design

PD Lec 16 Floor planning part 2 | VLSI | Physical Design

PD Lec 17 Floorplanning IO Placement part 3 | VLSI | Physical Design

PD Lec 18 Macro Placement Floor planning part 4 | VLSI | Physical Design

PD Lec 19 Macro Placement Guidelines Floor planning part 5 | VLSI | Physical Design

PD Lec 20 Macro Channel Spacing Estimation Floor planning part 6 | VLSI | Physical Design

PD Lec 21 Macro Placement Guidelines Floor planning part 7 | VLSI | Physical Design

PD Lec 22 Blockages and Keep out Margin | Floor planning | VLSI | Physical Design

PD Lec 23 Macro placement issues | | Floor planning | VLSI | Physical Design

PD Lec 24 Power planning and power mesh creation| Floor planning | VLSI | Physical Design

PD Lec 25 Physical Only Cells | Floor planning | VLSI | Physical Design

PD Lec 26 Sanity Checks 1 | Floor planning | VLSI | Physical Design

PD Lec 27 Sanity Checks 2 | Floor planning | VLSI | Physical Design

PD Lec 28 Sanity Checks 3 | Floor planning | VLSI | Physical Design

PD Lec 29 Cell Orientation and Flipping | Placement | VLSI | Physical Design

PD Lec 30 Interview Questions | VLSI | Physical Design

PD Lec 31 Introduction to Placement | VLSI | Physical Design

PD Lec 32 Placement of std cells | VLSI | Physical Design

PD Lec 33 Placement and Optimization | VLSI | Physical Design

PD Lec 34 place opt understanding | VLSI | Physical Design

PD Lec 35 Scan Chain Optimization | VLSI | Physical Design

PD Lec 36 Cell Density of std cells | VLSI | Physical Design

PD Lec 37 Pin Density of std cells | VLSI | Physical Design

PD Lec 38 Global Route Congestion | VLSI | Physical Design

PD Lec 39 CMOS Latch Up | VLSI | Physical Design

PD Lec 40 Well Tap Cell | VLSI | Physical Design

PD Lec 42 SVT LVT HVT Cell variants | VLSI | Physical Design

PD Lec 41 Tie Cell | tie low| tie high | VLSI | Physical Design

PD Lec 43 Timing Fixes in placement | Part 1 | VLSI | Physical Design

PD Lec 44 Timing Fixes in placement | Part 2 | VLSI | Physical Design

PD Lec 45 Spare Cells | Physical Only Cells | VLSI | Physical Design

PD Lec 46 Useful Skew | Timing Fixes in placement | VLSI | Physical Design

PD Lec 47 concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design

PD Lec 48 Interview Questions | placement | VLSI | Physical Design

PD Lec 49 Introduction to CTS | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 50 Clock Tree Synthesis | CTS | VLSI | Physical Design

PD Lec 51 How to balance skew and latency | CTS | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 52 CTS Algorithms | CTS | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 53 CTS Constraints | Spec File | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 54 CTS Exceptions | Float pin | Stop Pin | Exclude Pin | VLSI | Physical Design

PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design

PD Lec 56 Clock Gating Checks | CGC Paths | CTS | VLSI | Physical Design

PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design

PD Lec 58 Integrated Clock Gates | ICG | CTS | VLSI | Physical Design

PD Lec 59 Master Generated and Virtual Clocks | Type of clocks | VLSI | Physical Design

PD Lec 60 What is crosstalk | CTS | VLSI | Physical Design

PD Lec 61 Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design

PD Lec 62 CTS Analysis | VLSI | Physical Design

PD Lec 63 Post CTS Optimization | VLSI | Physical Design

PD Lec 64 Skew Groups | CTS | VLSI | Physical Design

PD Lec 65 Introduction to Routing | VLSI | Physical Design

PD Lec 66 Routing Concepts | VLSI | Physical Design

PD Lec 67 Global and Detail Routing | VLSI | Physical Design

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