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VLSI Physical Design basics

Engineering

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PD Lec 1 Introduction to Physical Design | Tutorial | VLSI

PD Lec 2 CMOS Basics part 1 | Tutorial | VLSI | Physical Design

PD Lec 3 CMOS Basics part 2 | Tutorial | VLSI | Physical Design

PD Lec 4 CMOS Basics part 3 | Tutorial | VLSI | Physical Design

PD Lec 5 Logic Gate Conversion | Tutorial | VLSI | Physical Design

PD Lec 6 CMOS basics part 4 | Tutorial | VLSI | Physical Design

PD Lec 7 Physical Design Inputs Overview | Tutorial | VLSI | Physical Design

PD Lec 8 Netlists | PD Inputs part 2 | VLSI | Physical Design

PD Lec 9 Timing Library | libs | PD Inputs part 3 | VLSI | Physical Design

PD Lec 10 LEF File | PD Inputs part 4 | VLSI | Physical Design

PD Lec 11 Constraints File | PD Inputs part 4 | VLSI | Physical Design

PD Lec 12 Technology File | Tech File | PD Inputs part 5 | VLSI | Physical Design

PD Lec 13 DEF File | PD Inputs part 6 | VLSI | Physical Design

PD Lec 14 Import Design | Milky Way Library | VLSI | Physical Design

PD Lec 15 Floor planning part 1 | VLSI | Physical Design

PD Lec 16 Floor planning part 2 | VLSI | Physical Design

PD Lec 17 Floorplanning IO Placement part 3 | VLSI | Physical Design

PD Lec 18 Macro Placement Floor planning part 4 | VLSI | Physical Design

PD Lec 19 Macro Placement Guidelines Floor planning part 5 | VLSI | Physical Design

PD Lec 20 Macro Channel Spacing Estimation Floor planning part 6 | VLSI | Physical Design

PD Lec 21 Macro Placement Guidelines Floor planning part 7 | VLSI | Physical Design

PD Lec 22 Blockages and Keep out Margin | Floor planning | VLSI | Physical Design

PD Lec 23 Macro placement issues | | Floor planning | VLSI | Physical Design

PD Lec 24 Power planning and power mesh creation| Floor planning | VLSI | Physical Design

PD Lec 25 Physical Only Cells | Floor planning | VLSI | Physical Design

PD Lec 26 Sanity Checks 1 | Floor planning | VLSI | Physical Design

PD Lec 27 Sanity Checks 2 | Floor planning | VLSI | Physical Design

PD Lec 28 Sanity Checks 3 | Floor planning | VLSI | Physical Design

PD Lec 29 Cell Orientation and Flipping | Placement | VLSI | Physical Design

PD Lec 30 Interview Questions | VLSI | Physical Design

PD Lec 31 Introduction to Placement | VLSI | Physical Design

PD Lec 32 Placement of std cells | VLSI | Physical Design

PD Lec 33 Placement and Optimization | VLSI | Physical Design

PD Lec 34 place opt understanding | VLSI | Physical Design

PD Lec 35 Scan Chain Optimization | VLSI | Physical Design

PD Lec 36 Cell Density of std cells | VLSI | Physical Design

PD Lec 37 Pin Density of std cells | VLSI | Physical Design

PD Lec 38 Global Route Congestion | VLSI | Physical Design

PD Lec 39 CMOS Latch Up | VLSI | Physical Design

PD Lec 40 Well Tap Cell | VLSI | Physical Design

PD Lec 42 SVT LVT HVT Cell variants | VLSI | Physical Design

PD Lec 41 Tie Cell | tie low| tie high | VLSI | Physical Design

PD Lec 43 Timing Fixes in placement | Part 1 | VLSI | Physical Design

PD Lec 44 Timing Fixes in placement | Part 2 | VLSI | Physical Design

PD Lec 45 Spare Cells | Physical Only Cells | VLSI | Physical Design

PD Lec 46 Useful Skew | Timing Fixes in placement | VLSI | Physical Design

PD Lec 47 concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design

PD Lec 48 Interview Questions | placement | VLSI | Physical Design

PD Lec 49 Introduction to CTS | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 50 Clock Tree Synthesis | CTS | VLSI | Physical Design

PD Lec 51 How to balance skew and latency | CTS | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 52 CTS Algorithms | CTS | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 53 CTS Constraints | Spec File | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 54 CTS Exceptions | Float pin | Stop Pin | Exclude Pin | VLSI | Physical Design

PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design

PD Lec 56 Clock Gating Checks | CGC Paths | CTS | VLSI | Physical Design

PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design

PD Lec 58 Integrated Clock Gates | ICG | CTS | VLSI | Physical Design

PD Lec 59 Master Generated and Virtual Clocks | Type of clocks | VLSI | Physical Design

PD Lec 60 What is crosstalk | CTS | VLSI | Physical Design

PD Lec 61 Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design

PD Lec 62 CTS Analysis | VLSI | Physical Design

PD Lec 63 Post CTS Optimization | VLSI | Physical Design

PD Lec 64 Skew Groups | CTS | VLSI | Physical Design

PD Lec 65 Introduction to Routing | VLSI | Physical Design

PD Lec 66 Routing Concepts | VLSI | Physical Design

PD Lec 67 Global and Detail Routing | VLSI | Physical Design

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4.5
57 Reviews
VANAPARTHI SOUJANYA

Excellent explanation 2025-09-27

Rupesh Kumar

he teaches idea is very good 2025-09-21

Indraja

Explanation was very excellent. Explaining with short videos that idea was nice .overall good course simply and short 2025-09-17

SIJIN SAJEEV

Great Experience 2025-09-08

Pratheesh.G R.govindraj

good 2025-08-30

Yuvasri S

good 2025-08-21

Srujankumar Adappa Singashetti

It's good 2025-08-20

ABUZAR YASEEN

It was a good course. 2025-07-30

Nikhith Gajawada

Good 2025-07-08

Garipelli Vyshnavi

It is excellent course 2025-07-08

Vamshi Chary

good 2025-06-29

Putluru Naga Lakshmi

Good 2025-06-25

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