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PD Lec 6 CMOS basics part 4 | Tutorial | VLSI | Physical Design

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Lessons List | 67 Lesson
PD Lec 1 Introduction to Physical Design | Tutorial | VLSI
00:03:44

PD Lec 1 Introduction to Physical Design | Tutorial | VLSI
PD Lec 2 CMOS Basics part 1 | Tutorial | VLSI | Physical Design
00:05:43

PD Lec 2 CMOS Basics part 1 | Tutorial | VLSI | Physical Design
PD Lec 3 CMOS Basics part 2 | Tutorial | VLSI | Physical Design
00:08:29

PD Lec 3 CMOS Basics part 2 | Tutorial | VLSI | Physical Design
PD Lec 4 CMOS Basics part 3 | Tutorial | VLSI | Physical Design
00:07:05

PD Lec 4 CMOS Basics part 3 | Tutorial | VLSI | Physical Design
PD Lec 5 Logic Gate Conversion | Tutorial | VLSI | Physical Design
00:07:01

PD Lec 5 Logic Gate Conversion | Tutorial | VLSI | Physical Design
PD Lec 6 CMOS basics part 4 | Tutorial | VLSI | Physical Design
00:07:54

PD Lec 6 CMOS basics part 4 | Tutorial | VLSI | Physical Design
PD Lec 7 Physical Design Inputs Overview | Tutorial | VLSI | Physical Design
00:06:17

PD Lec 7 Physical Design Inputs Overview | Tutorial | VLSI | Physical Design
PD Lec 8 Netlists | PD Inputs part 2 | VLSI | Physical Design
00:04:37

PD Lec 8 Netlists | PD Inputs part 2 | VLSI | Physical Design
PD Lec 9 Timing Library | libs | PD Inputs part 3 | VLSI | Physical Design
00:11:03

PD Lec 9 Timing Library | libs | PD Inputs part 3 | VLSI | Physical Design
PD Lec 10 LEF File | PD Inputs part 4 | VLSI | Physical Design
00:06:22

PD Lec 10 LEF File | PD Inputs part 4 | VLSI | Physical Design
PD Lec 11 Constraints File | PD Inputs part 4 | VLSI | Physical Design
00:13:55

PD Lec 11 Constraints File | PD Inputs part 4 | VLSI | Physical Design
PD Lec 12 Technology File | Tech File | PD Inputs part 5 | VLSI | Physical Design
00:04:07

PD Lec 12 Technology File | Tech File | PD Inputs part 5 | VLSI | Physical Design
PD Lec 13 DEF File | PD Inputs part 6 | VLSI | Physical Design
00:09:29

PD Lec 13 DEF File | PD Inputs part 6 | VLSI | Physical Design
PD Lec 14 Import Design | Milky Way Library | VLSI | Physical Design
00:08:58

PD Lec 14 Import Design | Milky Way Library | VLSI | Physical Design
PD Lec 15 Floor planning part 1 | VLSI | Physical Design
00:07:21

PD Lec 15 Floor planning part 1 | VLSI | Physical Design
PD Lec 16 Floor planning part 2 | VLSI | Physical Design
00:07:01

PD Lec 16 Floor planning part 2 | VLSI | Physical Design
PD Lec 17 Floorplanning IO Placement part 3 | VLSI | Physical Design
00:14:31

PD Lec 17 Floorplanning IO Placement part 3 | VLSI | Physical Design
PD Lec 18 Macro Placement Floor planning part 4 | VLSI | Physical Design
00:14:21

PD Lec 18 Macro Placement Floor planning part 4 | VLSI | Physical Design
PD Lec 19 Macro Placement Guidelines Floor planning part 5 | VLSI | Physical Design
00:07:59

PD Lec 19 Macro Placement Guidelines Floor planning part 5 | VLSI | Physical Design
PD Lec 20 Macro Channel Spacing Estimation Floor planning part 6 | VLSI | Physical Design
00:05:21

PD Lec 20 Macro Channel Spacing Estimation Floor planning part 6 | VLSI | Physical Design
PD Lec 21 Macro Placement Guidelines Floor planning part 7 | VLSI | Physical Design
00:08:48

PD Lec 21 Macro Placement Guidelines Floor planning part 7 | VLSI | Physical Design
PD Lec 22 Blockages and Keep out Margin | Floor planning | VLSI | Physical Design
00:06:32

PD Lec 22 Blockages and Keep out Margin | Floor planning | VLSI | Physical Design
PD Lec 23 Macro placement issues | | Floor planning | VLSI | Physical Design
00:05:52

PD Lec 23 Macro placement issues | | Floor planning | VLSI | Physical Design
PD Lec 24 Power planning and power mesh creation| Floor planning | VLSI | Physical Design
00:07:35

PD Lec 24 Power planning and power mesh creation| Floor planning | VLSI | Physical Design
PD Lec 25 Physical Only Cells | Floor planning | VLSI | Physical Design
00:09:24

PD Lec 25 Physical Only Cells | Floor planning | VLSI | Physical Design
PD Lec 26 Sanity Checks 1 | Floor planning | VLSI | Physical Design
00:04:58

PD Lec 26 Sanity Checks 1 | Floor planning | VLSI | Physical Design
PD Lec 27 Sanity Checks 2 | Floor planning | VLSI | Physical Design
00:07:49

PD Lec 27 Sanity Checks 2 | Floor planning | VLSI | Physical Design
PD Lec 28 Sanity Checks 3 | Floor planning | VLSI | Physical Design
00:05:40

PD Lec 28 Sanity Checks 3 | Floor planning | VLSI | Physical Design
PD Lec 29 Cell Orientation and Flipping | Placement | VLSI | Physical Design
00:08:44

PD Lec 29 Cell Orientation and Flipping | Placement | VLSI | Physical Design
PD Lec 30 Interview Questions | VLSI | Physical Design
00:05:49

PD Lec 30 Interview Questions | VLSI | Physical Design
PD Lec 31 Introduction to Placement | VLSI | Physical Design
00:06:15

PD Lec 31 Introduction to Placement | VLSI | Physical Design
PD Lec 32 Placement of std cells | VLSI | Physical Design
00:05:20

PD Lec 32 Placement of std cells | VLSI | Physical Design
PD Lec 33 Placement and Optimization | VLSI | Physical Design
00:06:23

PD Lec 33 Placement and Optimization | VLSI | Physical Design
PD Lec 34 place opt understanding | VLSI | Physical Design
00:07:34

PD Lec 34 place opt understanding | VLSI | Physical Design
PD Lec 35 Scan Chain Optimization | VLSI | Physical Design
00:09:24

PD Lec 35 Scan Chain Optimization | VLSI | Physical Design
PD Lec 36 Cell Density of std cells | VLSI | Physical Design
00:07:16

PD Lec 36 Cell Density of std cells | VLSI | Physical Design
PD Lec 37 Pin Density of std cells | VLSI | Physical Design
00:05:04

PD Lec 37 Pin Density of std cells | VLSI | Physical Design
PD Lec 38 Global Route Congestion | VLSI | Physical Design
00:05:42

PD Lec 38 Global Route Congestion | VLSI | Physical Design
PD Lec 39 CMOS Latch Up | VLSI | Physical Design
00:09:17

PD Lec 39 CMOS Latch Up | VLSI | Physical Design
PD Lec 40 Well Tap Cell | VLSI | Physical Design
00:04:32

PD Lec 40 Well Tap Cell | VLSI | Physical Design
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Ok
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good
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Dusa Amulya 

It is very useful platform
2025-11-30

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goood
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It was really good
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good
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Nyc
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Course Description

VLSI Physical Design course in hindi, in this course explores the intricacies of chip layout, placement, and routing for efficient and high-performance integrated circuit design
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