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Computer Networks Part One LANs and WANs

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Lessons List | 38 Lesson
Personal Computer Architecture
00:18:06

Personal Computer Architecture
Graphics Processing Unit GPU
00:09:31

Graphics Processing Unit GPU
Fetch Decode Execute Cycle and the Accumulator
00:01:52

Fetch Decode Execute Cycle and the Accumulator
Fetch Decode Execute Cycle in more detail
00:07:55

Fetch Decode Execute Cycle in more detail
Processor Addressing Modes
00:10:27

Processor Addressing Modes
Introduction to Logic Gates
00:07:14

Introduction to Logic Gates
Logic Gate Combinations
00:12:12

Logic Gate Combinations
Logic Gate Expressions
00:13:00

Logic Gate Expressions
Logic Gates and the Ripple Carry Adder
00:09:25

Logic Gates and the Ripple Carry Adder
Dynamic Random Access Memory DRAM Part 1 Memory Cell Arrays
00:10:28

Dynamic Random Access Memory DRAM Part 1 Memory Cell Arrays
Dynamic Random Access Memory DRAM Part 2 Read and Write Cycles
00:10:36

Dynamic Random Access Memory DRAM Part 2 Read and Write Cycles
Dynamic Random Access Memory DRAM Part 3 Binary Decoders
00:03:50

Dynamic Random Access Memory DRAM Part 3 Binary Decoders
Dynamic Random Access Memory DRAM Part 4 Multiplexers and Demultiplexers
00:08:41

Dynamic Random Access Memory DRAM Part 4 Multiplexers and Demultiplexers
Dynamic Random Access Memory DRAM Part 5 DIMM Organisation
00:07:38

Dynamic Random Access Memory DRAM Part 5 DIMM Organisation
Dynamic Random Access Memory DRAM Part 6 Burst Mode and Bank Interleaving
00:12:10

Dynamic Random Access Memory DRAM Part 6 Burst Mode and Bank Interleaving
Dynamic Random Access Memory DRAM Part 7 Memory Address Mapping
00:05:51

Dynamic Random Access Memory DRAM Part 7 Memory Address Mapping
Computer Networks Part One LANs and WANs
00:06:10

Computer Networks Part One LANs and WANs
Computer Networks Part Two Network Hardware
00:09:21

Computer Networks Part Two Network Hardware
Computer Networks Part Three Ethernet
00:03:53

Computer Networks Part Three Ethernet
Latches and Flip Flops 1 The SR Latch
00:12:14

Latches and Flip Flops 1 The SR Latch
Latches and Flip Flops 2 The Gated SR Latch
00:09:33

Latches and Flip Flops 2 The Gated SR Latch
Latches and Flip Flops 3 The Gated D Latch
00:07:48

Latches and Flip Flops 3 The Gated D Latch
Latches and Flip Flops 4 – The Clocked D Latch
00:11:40

Latches and Flip Flops 4 – The Clocked D Latch
Latches and Flip Flops 5 – D Type Flip Flop
00:13:50

Latches and Flip Flops 5 – D Type Flip Flop
Karnaugh Maps – Introduction
00:13:45

Karnaugh Maps – Introduction
Karnaugh Maps with 4 Variables
00:04:59

Karnaugh Maps with 4 Variables
Karnaugh Maps – Simplify Boolean Expressions
00:07:26

Karnaugh Maps – Simplify Boolean Expressions
The Hard Drive Buffer
00:04:20

The Hard Drive Buffer
RISC versus CISC
00:12:40

RISC versus CISC
Little Man Computer 1 Introduction
00:20:09

Little Man Computer 1 Introduction
Little Man Computer 2 Branching Code
00:17:30

Little Man Computer 2 Branching Code
Little Man Computer 3 Loops
00:22:45

Little Man Computer 3 Loops
Harvard Architecture versus Von Neumann Architecture
00:05:18

Harvard Architecture versus Von Neumann Architecture
Byte Order Endianness
00:13:16

Byte Order Endianness
OLD The Accumulator Register
00:09:46

OLD The Accumulator Register
The Fetch Decode Execute Cycle
00:16:45

The Fetch Decode Execute Cycle
The Accumulator
00:09:48

The Accumulator
Pipeline Architecture
00:08:23

Pipeline Architecture

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